Because metal-oxide-semiconductor field effect transistors (MOSFETs) provide relatively simple operation and high integration density, MOSFETs are widely used for digital electronic devices such as memory devices. A conventional MOSFET structure includes a gate electrode on a semiconductor substrate, source/drain impurity regions formed in the semiconductor substrate at opposite sides of the gate electrode, and a gate insulating layer between the semiconductor substrate and the gate electrode. Structures, operations, and fabrication of MOSFET devices are explained in “MOS Devices and NMOS process integration (chapter5)” of “Silicon Processing for the VLSI Era, Vol. 2-Process Integration,” 2nd ed., Lattice Press: Sunset Beach Calif., 1986, by Stanley Wolf.
As described by Wolf, a conventional method of fabricating a MOSFET includes steps of sequentially forming a gate insulating layer and a gate electrode on a semiconductor substrate and performing an ion implantation using the gate electrode as a mask. The impurity regions formed by the ion implantation provide source and drain electrodes of the MOSFET. In addition, a thermal treatment may be performed during the ion implantation to cure lattice defects of the semiconductor substrate and to activate the implanted impurities. When the thermal treatment is performed for a long time however, implanted impurities may diffuse under the gate electrode resulting in a short channel effect such that a channel length of the MOSFET is reduced. Process variations of the thermal treatment, such as a temperature and/or a time, should be reduced to reduce short channel effects. Short channel effects may result, however, from a process sequence of forming the gate electrode before forming the source/drain regions. The short channel effect may thus occur even if the conditions of the thermal treatment are controlled.
As semiconductor devices become more highly integrated, there is a continuing need for source/drain electrodes having shallow junction structures. An elevated source/drain structure using an epitaxial growth technique has been proposed to form shallow junction structure, as disclosed at Page 158 of Wolf. However, the epitaxial growth technique may have technical disadvantages, such as complexity, high cost, and difficulty of control.